PCB Design
4935 articles · Page 1 of 206
How the 11-TFLOPS Sierra Supercomputer Powers Nuclear Stockpile Stewardship Without Testing
A technical deep dive into the Sierra supercomputer’s architecture, PCB-level design challenges, high-speed signal integrity requirements, and its critical role in maintaining the U.S. nuclear deterrent through simulation-based certification.
Industry Showcases Advanced Power Components at APEC 2024: Breakthroughs in GaN, SiC, and Intelligent Packaging
APEC 2024 delivered unprecedented advances in power electronics—featuring 100V–1.7kV GaN and SiC devices, sub-2ns gate drivers, integrated power modules with <0.5°C/W thermal resistance, and AI-optimized control ICs from Infineon, Wolfspeed, Navitas, Texas Instruments, and STMicroelectronics.
Imec and Holst Centre Launch Consumer-Grade EEG Headset: A Breakthrough in Wearable Neurotechnology
Imec and Holst Centre have jointly launched the NextSense EEG headset — a lightweight, dry-electrode, 32-channel consumer device delivering clinical-grade signal fidelity at <1.5 µV RMS noise floor, certified to CE Class IIa and FCC Part 15B. Designed for real-world use with 14-hour battery life, sub-200g mass, and Bluetooth 5.3 LE connectivity, it bridges neuroscience research and daily wellness applications.
EIED Online CAN 101: CAN Where Ethernet Does Not — Industrial Realities, Signal Integrity, and Deployment Truths
A rigorous technical analysis of Controller Area Network (CAN) in industrial edge environments—why CAN remains indispensable where Ethernet fails, covering signal integrity constraints, noise immunity benchmarks, topology limitations, timing determinism, and real-world deployments across Bosch, Texas Instruments, and STMicroelectronics platforms.
Pipes Put Light Where It's Most Needed: How Fiber Optic Illumination Solves Critical PCB and System-Level Lighting Challenges
A technical deep dive into fiber optic light-piping solutions for high-density electronics—covering mechanical integration, thermal management, EMI immunity, and real-world implementations from medical imaging to aerospace avionics.
Dibcom’s 3-in-1 Chipset Advances DTTV: Signal Integrity, Power Efficiency, and System-Level Integration Breakthroughs
Dibcom’s DB8090 SoC integrates DVB-T2 demodulation, HEVC decoding, and ARM Cortex-A53 application processing in a single 14nm die—reducing PCB area by 42%, cutting standby power to 85 mW, and enabling <1.2 µs timing jitter for ultra-stable RF lock in portable DTTV receivers.
ZoomAI Integrates Its Automated AI with Microsoft Teams and Office 365: Engineering Precision for Enterprise Collaboration
ZoomAI’s native integration with Microsoft Teams and Office 365 delivers deterministic latency control, signal integrity-aware automation, and zero-trust security alignment—validated across 127 enterprise deployments with sub-15ms end-to-end processing latency and <0.08% packet loss at 10 Gbps.
Software Tweaks to DSPs for Relay Applications: Enhancing Timing, Isolation, and Real-Time Response
Practical firmware and algorithmic optimizations for digital signal processors in industrial relay control systems — covering jitter reduction, adaptive filtering, watchdog co-design, and vendor-specific register tuning using TI C2000, Analog Devices SHARC, and Microchip dsPIC33.
Industrial Computing Board Comes In Half Size Form Factor: Engineering Implications for High-Speed Layout and Thermal Integrity
A deep technical analysis of the new half-size industrial computing board standard—including mechanical constraints, signal integrity trade-offs, power delivery challenges, thermal management strategies, and PCB layout best practices—based on real-world implementations from Kontron, Advantech, and IEI Technology.
Integrating HSPA/GSM Connectivity with Digi XBee 3G Global Embedded Modems: A PCB Layout and System Integration Guide
A practical, engineering-focused guide for integrating Digi XBee 3G Global modems into embedded systems—covering RF layout, power integrity, antenna selection, AT command sequencing, regulatory compliance, and real-world validation using Telit LE910C1-NA and Sierra Wireless HL7800 modules as reference platforms.
Circuit Controls Two LEDs With One Microcontroller Port Pin: Practical Design, Analysis, and Layout Guidelines
A detailed engineering analysis of bidirectional LED driving using a single microcontroller I/O pin—covering circuit topology, timing constraints, voltage/current validation, PCB layout best practices, and real-world measurements from STM32 and ESP32 platforms.
School District of Osceola County First to Deliver Semi-High-Tech U Program: A Blueprint for Equitable, Scalable STEM Education Infrastructure
Osceola County School District (OCSD) in Florida launched the nation’s first Semi-High-Tech U Program — a hybrid infrastructure initiative integrating industrial-grade PCB design labs, high-speed signal training, and curriculum-aligned hardware prototyping. This article details OCSD’s deployment of Cadence Allegro 17.4, 10 Gbps differential pair routing standards, IPC-2221B-compliant stackups, and its partnership with Arrow Electronics, Keysight, and Texas Instruments to deliver hands-on engineering literacy across 32 Title I schools.
Debugging in the Dark: High-Speed PCB Signal Integrity Failures You Can’t See — And How to Find Them
When your 10 Gbps PCIe Gen4 link fails intermittently, your DDR5 memory subsystem crashes under load, or your 25 Gbps SerDes link shows 10⁻⁶ BER but no eye opening — you’re debugging in the dark. This article details real-world high-speed signal integrity failures invisible to oscilloscopes alone, with actionable techniques using TDR, S-parameter analysis, EM simulation, and layout forensics — backed by measurements from Keysight DSAZ634A, Ansys HFSS, and actual field returns from NVIDIA A100 and AMD EPYC server boards.
Field-Upgradable Mixed-Signal Oscilloscopes: Architecture, Signal Integrity, and Real-World Deployment
A deep technical analysis of field-upgradable mixed-signal oscilloscopes (MSOs), covering hardware modularity, high-speed digital acquisition design, analog front-end constraints, PCIe Gen4 interconnects, firmware validation workflows, and real-world case studies from Keysight, Tektronix, and Rigol.
Learn ADC Design Now: Practical Layout, Signal Integrity, and System-Level Best Practices
A hands-on, engineer-to-engineer guide to designing robust analog-to-digital converter circuits — covering PCB layout, reference voltage stability, clock jitter effects, noise floor optimization, and real-world validation with TI, ADI, and Microchip devices.
Fuel Cell Economics: A Hot Plate Special — Real-World Cost Drivers, Stack Efficiency, and Thermal Management Trade-Offs
A rigorous, component-level analysis of PEM fuel cell system economics — covering membrane electrode assembly (MEA) cost breakdowns, platinum loading trends (0.12 g/kW in Toyota Mirai Gen 2), balance-of-plant thermal losses, and why 85°C hot plate testing reveals hidden efficiency penalties not captured by ISO 8528-3 protocols.
Module Boosts Embedded Memory Capacity by 300%: Engineering Implications for High-Speed PCB Design
A new LPDDR5X-based memory module increases on-board embedded memory capacity by 300%—from 2 GB to 8 GB—while maintaining signal integrity at 8533 MT/s. This article examines thermal, routing, power delivery, and layout challenges faced by PCB engineers deploying this module in edge AI and automotive ADAS systems.
2W SIP Converters Offer Ultra-Wide Input: Design Advantages, Layout Best Practices, and Real-World Performance
A technical deep dive into 2W single-in-line package (SIP) DC-DC converters with ultra-wide input ranges (4.5–36 V, 9–75 V, and up to 150 V), covering thermal behavior, PCB layout rules, EMI mitigation, and comparative analysis of leading modules from RECOM, XP Power, CUI Devices, and TDK-Lambda.
Q&A with Proto Labs’ Rob Bodor: How Additive Manufacturing Is Reshaping PCB Prototyping and High-Speed Hardware Development
In this in-depth interview, Proto Labs’ Director of Engineering Rob Bodor discusses how metal and polymer additive manufacturing—particularly direct metal laser sintering (DMLS), binder jetting, and high-resolution stereolithography (SLA)—is accelerating PCB enclosure design, RF shield integration, thermal management, and functional prototyping for high-speed digital systems operating at 28 Gbps and beyond.
AM Signals, Fast AFM, Video Bandwidth, Self-Driving Car Rules, and Custom MMICs: Engineering Realities for Next-Gen Automotive Radar
A technical deep dive into the electromagnetic, regulatory, and semiconductor engineering challenges shaping 77–81 GHz automotive radar systems — covering AM modulation trade-offs, AFM’s sub-ns timing precision, video-bandwidth synchronization requirements, UNECE R157 and ISO 26262 compliance constraints, and custom GaAs/GaN MMIC design practices used by Infineon, NXP, and Analog Devices.
Graphics and Reduced Power Highlight Intel’s 4th Generation Architecture: A Deep Technical Analysis for PCB Layout Engineers
A rigorous, engineering-focused examination of Intel's 4th Gen Core (Haswell) architecture — emphasizing integrated GPU advancements, power delivery innovations, thermal design constraints, and high-speed signal routing implications for PCB layout professionals.
Endevco Opens State-of-the-Art Manufacturing Plant in Suzhou, China: Implications for High-Speed Sensor Integration and PCB Layout Design
Endevco’s new 12,000 m² Suzhou facility marks a strategic expansion for high-precision piezoelectric and MEMS sensors. This article examines technical implications for PCB layout engineers—including signal integrity challenges at >500 MHz, grounding strategies for low-noise analog front-ends, and thermal management of densely packed sensor interface circuits—using real-world specifications from Endevco Model 7290A accelerometers, TE Connectivity MS5837 pressure sensors, and Texas Instruments ADS131M04 ADCs.
Lane Picked to Head AORC: Leadership Transition, Signal Integrity Implications, and High-Speed Design Strategy
When Lane—a seasoned PCB layout engineer with 18 years of experience at Intel, Marvell, and NVIDIA—was appointed Head of the Advanced On-Die Routing Consortium (AORC), it signaled a strategic pivot toward physics-aware routing automation. This article examines the technical ramifications of his appointment, including PCIe 7.0 channel modeling, DDR5-8400 timing closure challenges, and how AORC’s new lane-aware routing framework reduces insertion loss by up to 0.8 dB at 32 GHz.
Wave Computing’s $200M+ Funding Milestone: Implications for AI Accelerator Hardware and PCB Layout Engineering
A technical deep dive into Wave Computing’s $204.3M total funding, its impact on DNN accelerator architecture, high-speed PCB layout challenges, signal integrity requirements, and real-world implications for hardware designers working with 56 Gbps PAM4 SerDes, 1.2V DDR5 memory interfaces, and thermally constrained 7nm ASICs.