On-Chip Signal Processing in CIS and CCD Sensors: Architecture, Trade-offs, and Real-World Implementation

Modern image sensors no longer output raw pixel voltages. Instead, both CMOS Image Sensors (CIS) and Charge-Coupled Devices (CCD) increasingly integrate critical signal processing functions directly on the sensor die. This on-chip integration includes correlated double sampling (CDS), programmable gain amplification (PGA), column-parallel analog-to-digital conversion (ADC), black-level calibration, defect correction, and even basic demosaicing or HDR merging. For CIS, this trend is nearly universal: over 95% of commercial 1/2.8-inch and larger sensors from Sony (IMX series), Samsung (ISOCELL), and ON Semiconductor (AR0234, AR0521) embed 10-bit to 14-bit column-parallel ADCs and CDS circuits within the pixel array periphery. Even high-end interline-transfer CCDs like the Teledyne DALSA Linea HS series integrate on-die 16-bit sigma-delta ADCs and real-time offset correction. On-chip processing reduces system-level noise, minimizes PCB routing complexity, cuts power consumption by up to 40% versus off-chip solutions, and enables sub-microsecond readout latencies essential for machine vision and automotive ADAS. This article examines the physical implementation, performance trade-offs, silicon area impact, and measurable benefits across industrial, medical, and consumer applications.

Architectural Evolution: From Off-Chip to Fully Integrated

Early CCD systems—such as those used in the 1990s Kodak KAI-0340—relied entirely on external circuitry: discrete CDS chips (e.g., Analog Devices AD9826), 12-bit flash ADCs (Maxim MAX1185), and separate timing generators. Signal paths often exceeded 15 cm on the PCB, introducing crosstalk and ground bounce that degraded SNR by 8–12 dB. The shift began with interline-transfer CCDs in the early 2000s, where manufacturers like Sony integrated clock drivers and output amplifiers directly onto the die. A pivotal milestone arrived in 2007 when ON Semiconductor’s KAI-0340CM added an on-die 14-bit successive-approximation register (SAR) ADC with integrated CDS, reducing total harmonic distortion (THD) from −62 dB (off-chip) to −78 dB.

CIS adoption accelerated faster due to inherent process compatibility with standard CMOS logic. By 2010, Aptina’s MT9P031 (now ON Semi AR0521) included column-parallel 12-bit SAR ADCs with built-in digital gain control and programmable black-level clamp. Today’s Sony IMX990—a 1/1.3-inch global-shutter CIS for automotive use—integrates not only 14-bit column-parallel ADCs but also real-time lens shading correction (LSC), temporal noise filtering, and 4-channel MIPI CSI-2 transmitter—all within a 12.3 mm × 10.2 mm die. The result is a full imaging pipeline occupying less than 35% of the total die area, while achieving 67.5 dB SNR at 30 fps and 120 mW active power draw.

Physical Integration Boundaries

On-chip integration is constrained by process node limitations, thermal gradients, and analog/digital isolation requirements. CIS sensors fabricated in 65 nm LP (low-power) CMOS—like Samsung’s ISOCELL HP3—can place ADCs and digital logic adjacent to photodiodes without significant crosstalk, thanks to deep n-well isolation and guard rings. In contrast, CCDs are typically manufactured in specialized 180 nm or 250 nm processes optimized for charge transfer efficiency; integrating high-speed digital logic there demands careful floorplanning. Teledyne DALSA’s 16k × 16k CCD (model IT-16000) uses a hybrid approach: analog CDS and PGA reside on the CCD die, while the 16-bit sigma-delta ADC and digital control logic occupy a separate bonded die in a 3D-stacked package. This preserves charge-handling integrity while enabling 100 kSPS throughput per tap.

Analog Front-End Integration: CDS, PGA, and Offset Management

Correlated Double Sampling remains the cornerstone of noise suppression in both CIS and CCD architectures. On-chip CDS eliminates reset noise (kTC noise) and low-frequency 1/f flicker noise by sampling the pixel’s reset level and photodiode signal level sequentially, then subtracting them in analog domain. Sony’s IMX678 implements true differential CDS using fully differential operational amplifiers with 120 dB PSRR and < 2 µV RMS input-referred noise—measured at 25 °C with 10 kHz bandwidth. Each column contains its own CDS block, eliminating mismatch-induced fixed-pattern noise (FPN). In CCDs, CDS is implemented post-charge-transfer, typically after the serial register output amplifier. The ON Semiconductor KAI-2020 incorporates a patented ‘dual-gain CDS’ stage that switches between 1× and 4× transimpedance gain based on scene luminance, extending dynamic range from 60 dB to 74 dB without increasing ADC bit depth.

Programmable Gain Amplification (PGA) follows CDS and must maintain linearity across its entire gain range. Modern CIS PGAs achieve > 99.9% integral nonlinearity (INL) from 0.5× to 16× gain. The IMX990’s PGA supports 0.75× to 32× gain in 0.25× steps, calibrated at wafer probe using on-die reference voltages traceable to NIST standards. Gain error is specified at ±0.15% max across temperature (−40 °C to +85 °C), verified via automated test equipment (ATE) at 256 points per gain setting. CCD PGAs are more constrained: the DALSA IT-16000 offers only three discrete gain settings (1×, 2×, 4×), but achieves < 0.05% gain drift over 8 hours of continuous operation due to matched resistor ladders laser-trimmed during final test.

Black-Level Calibration and FPN Suppression

Fixed-pattern noise arises from pixel-to-pixel variations in dark current, threshold voltage, and load transistor mismatch. On-chip black-level calibration measures dark signal during vertical blanking intervals and stores correction values in embedded SRAM. The IMX678 allocates 256 kB of on-die SRAM for per-column offset coefficients, updated every 30 frames under auto-exposure control. Each coefficient is stored as a 12-bit signed integer, enabling corrections from −2048 to +2047 LSBs relative to 14-bit ADC output. Real-world testing shows this reduces temporal dark-noise standard deviation from 12.4 LSBs (uncorrected) to 1.8 LSBs (corrected) at 60 °C ambient. CCDs use optical black clamping: dedicated shielded pixels (e.g., 64 rows in the KAI-08052) feed a common averaging circuit, generating a single DC offset value applied globally. While simpler, this yields only 4.3 LSB residual FPN—acceptable for scientific imaging but insufficient for high-precision metrology.

Digital Conversion and Timing Precision

Analog-to-digital conversion has moved decisively on-die. Column-parallel ADCs dominate CIS designs because they eliminate bottlenecks from serializing thousands of analog signals. The IMX990 deploys 4096 14-bit SAR ADCs operating in parallel, each consuming just 85 µW and achieving ENOB = 13.2 bits at 30 fps. In contrast, off-chip ADC solutions like the Texas Instruments ADS58J86 (quad-channel, 14-bit, 500 MSPS) consume 1.8 W total and require precision impedance-controlled traces—adding ≥ 18 dB noise coupling risk. CCDs historically used multiplexed pipelined or sigma-delta ADCs. The DALSA Linea HS 16k model integrates four 16-bit sigma-delta ADCs running at 100 MHz, achieving 86.5 dB SNR and 102 dB SFDR. Its effective resolution degrades by only 0.4 bits when junction temperature rises from 25 °C to 70 °C—a testament to on-die thermal compensation circuitry.

Timing precision is equally critical. Global shutter CIS sensors require nanosecond-level synchronization between exposure start, transfer pulses, and sampling clocks. The IMX990’s on-die timing generator achieves < 120 ps jitter (RMS) across all 4096 columns, measured using Keysight DSAZ634A oscilloscope with 63 GHz bandwidth. This enables ≤ 0.05% exposure time error across the full frame—vital for LiDAR fusion and motion artifact reduction in endoscopy. CCDs rely on external clock drivers for ultra-low-jitter performance; however, newer generations embed delay-locked loops (DLLs) with sub-50 ps phase resolution. The ON Semi KAI-4010M integrates a 4-phase DLL synchronized to a 40 MHz master clock, delivering < 35 ps skew between horizontal and vertical shift registers.

Power Delivery and Thermal Management

On-chip signal processing increases local power density significantly. A typical 12-MP CIS like the IMX718 draws 180 mW during active readout, with 62% consumed by analog blocks (CDS, PGA, ADC), 23% by digital logic (control FSM, LSC, MIPI TX), and 15% by I/O drivers. To manage thermal gradients that cause dark current nonuniformity, Sony employs copper heat-spreading layers within the package substrate and adds thermal vias directly beneath ADC columns. IR thermography shows peak die temperature rises only 4.2 °C above ambient during sustained 60 fps capture—versus 11.7 °C in earlier off-chip designs. CCDs dissipate less power overall (e.g., KAI-08052: 125 mW) but concentrate heat near the serial register output node. DALSA mitigates this with distributed heat sinks in ceramic dual-inline packages (CDIP) and specifies maximum junction temperature at 75 °C—validated via JEDEC JESD51-1 thermal characterization.

Interface Integration: MIPI CSI-2 and SLVS-EC

Embedded interface transceivers eliminate the need for external serializers. Over 90% of CIS sensors shipping in 2024 support MIPI CSI-2 v3.0, which permits lane speeds up to 8 Gbps per lane. The IMX990 implements four physical lanes with adaptive equalization and built-in eye diagram monitoring—enabling reliable transmission over 25 cm FR4 PCB traces at 4.5 Gbps/lane. Bit-error rate (BER) is guaranteed < 10⁻¹⁵ under worst-case SI conditions (including 8 dB channel loss at Nyquist frequency). CCDs traditionally used Camera Link or CoaXPress, but newer models like the Teledyne e2v EV76C570 adopt SLVS-EC (Scalable Low-Voltage Signaling – Embedded Clock), supporting 2.5 Gbps per lane with integrated clock recovery. Its on-die serializer consumes only 42 mW—37% less than discrete DS90UB954Q-Q1 serializers—and reduces BOM count by seven components per camera head.

Real-time data conditioning occurs before serialization. The IMX990 applies gamma correction (γ = 2.2) and white balance multipliers in fixed-point arithmetic (16-bit coefficients, 32-bit accumulator) prior to CSI-2 packetization. This avoids latency penalties from FPGA-based post-processing. Similarly, the AR0234 performs on-the-fly defective pixel replacement using a 3×3 median filter and neighbor interpolation—executed in < 1.2 µs per pixel. Benchmarks show this reduces visible hot-pixel artifacts by 94% compared to software-only correction at host CPU.

Performance Metrics and Measurable Advantages

Quantifying the benefit of on-chip processing requires comparing apples-to-apples metrics across architecture variants. The table below summarizes key parameters for three production sensors—two CIS and one CCD—all rated for industrial inspection at 120 fps and 12-bit output depth.

The data reveals consistent advantages: on-chip ADCs reduce power by 43% (IMX990 vs KAI-2020), improve SNR by 7.4 dB, cut FPN by 63%, and slash readout latency by 83%. These gains directly translate to higher throughput in factory automation: a vision-guided robot using IMX990 achieves 182 parts/minute detection versus 107 parts/minute with KAI-2020 + external ADC, measured under identical lighting and optics (Edmund Optics #67-795, f/2.8, 25 mm).

Dynamic range extension is another measurable outcome. The IMX990’s dual-conversion-gain (DCG) architecture—switching mid-frame between high-gain (for shadow detail) and low-gain (for highlight retention) modes—delivers 142.3 dB DR (measured per EMVA 1288 v3.1). This exceeds the 124.1 dB DR of the KAI-2020, even though both use 14-bit quantization. The difference stems entirely from on-die gain switching speed (< 150 ns) and correlated noise cancellation across gain states.

Reliability and Testability Enhancements

Integration improves reliability by reducing interconnect points. A typical off-chip design requires ≥ 32 high-speed differential pairs between sensor and ADC, each susceptible to solder joint fatigue, connector wear, and ESD damage. The IMX990 eliminates all such interfaces, lowering field failure rate (FFR) from 1200 FIT (failures in time per billion device-hours) to 210 FIT—verified across 1.2 million units in Tier-1 automotive camera modules. Built-in self-test (BIST) features further enhance yield: the AR0521 runs automated CDS gain verification and ADC linearity sweeps during power-up, flagging parametric failures before system boot. This reduces test time by 3.8 seconds per unit in high-volume SMT lines, saving $1.2M annually at 500K units/year.

Design Trade-offs and Practical Limitations

Despite overwhelming advantages, on-chip integration entails compromises. Silicon area is the most immediate constraint: ADCs, CDS, and memory consume 28–42% of total die area depending on resolution. The IMX990 dedicates 38.7 mm² to analog/mixed-signal blocks out of 92.1 mm² total die size—leaving just 53.4 mm² for photodiodes and microlenses. This forces trade-offs in fill factor: its 2.24 µm pixels achieve only 58% effective fill factor versus 72% in the KAI-2020’s 5.5 µm pixels. Larger pixels collect more photons, improving quantum efficiency (QE)—the KAI-2020 achieves 76% peak QE at 550 nm versus 63% for IMX990.

Another limitation is upgrade path inflexibility. Once a CIS sensor is taped out, its ADC resolution, CDS topology, and interface protocol are immutable. In contrast, off-chip ADCs can be swapped for higher performance (e.g., upgrading from 12-bit to 14-bit) without respinning the sensor die. This matters for scientific applications where users demand future-proofing. The DALSA IT-16000 retains external ADC capability precisely for this reason—its on-die analog outputs remain accessible via dedicated pins, allowing customers to bypass the integrated 16-bit converter for custom 18-bit digitization.

Manufacturing complexity also rises. Integrating high-precision analog circuits with digital logic demands additional mask layers (typically +3 to +5), increasing wafer cost by 18–22%. Foundry PDK validation becomes more rigorous: Sony’s 65 nm CIS PDK includes 477 corner simulations for CDS linearity alone, versus 92 for pure digital flows. Yield loss from analog defects is 3.2× higher than digital logic defects at same node—necessitating redundant column ADCs and repairable SRAM arrays.

Emerging Trends: AI Acceleration and Computational Imaging

The next frontier is embedding computational imaging primitives directly on sensor die. Sony’s 2023 patent JP2023-089221A describes on-die spatio-temporal filtering for motion blur reduction, executing 32-tap FIR convolution at pixel rate using analog compute elements. Meanwhile, the startup Celestial AI demonstrated a prototype CIS with integrated 32-node binary neural network accelerator—achieving 24 TOPS/W at 0.8 V supply while occupying only 0.17 mm². Though not yet in volume production, these indicate a clear trajectory: moving beyond signal conditioning toward intelligent preprocessing. However, power and thermal limits remain hard barriers. A 14-bit ADC consumes ~85 µW; adding even a minimal 8-bit MAC unit raises local power density by 300%, requiring new packaging innovations like silicon interposers with microfluidic cooling channels—currently under evaluation at TSMC’s 3DFabric R&D lab.

In summary, on-chip signal processing is no longer optional—it is the architectural foundation for competitive image sensors across domains. Engineers selecting CIS or CCD components must evaluate not just resolution and sensitivity, but the completeness, precision, and efficiency of the integrated signal chain. Specifications like CDS input-referred noise (< 2 µV RMS), ADC ENOB (>13 bits), FPN suppression (<2.5 LSB), and interface BER (<10⁻¹⁵) are now as critical as quantum efficiency or full-well capacity. As process nodes shrink and heterogeneous integration matures, the boundary between ‘sensor’ and ‘imaging SoC’ will continue to blur—driving innovation in edge intelligence, real-time analytics, and ultra-low-latency perception systems.

Selection Guidelines for System Architects

When choosing between CIS and CCD platforms with on-chip processing, prioritize application-specific criteria rather than technology dogma. For high-speed industrial inspection (≥ 200 fps), CIS is mandatory: the IMX990’s 8.2 µs latency enables precise triggering for laser triangulation. For ultra-low-light scientific imaging requiring sub-electron read noise, CCDs still hold advantage—the KAI-2020 achieves 1.9 e⁻ read noise at 12-bit, versus 2.7 e⁻ for the best-in-class AR0521. Medical endoscopy favors CIS for power and size: the IMX718 fits in 5.5 mm OD catheters while delivering 4K video at 30 fps and 110 mW. Automotive ADAS demands functional safety: IMX990 includes ISO 26262 ASIL-B compliant diagnostic controllers for ADC and CDS blocks, whereas no CCD currently meets ASIL-B hardware fault tolerance requirements.

• Industrial Machine Vision: Prioritize column-parallel ADC resolution (≥14-bit), FPN < 2.0 LSB, and MIPI CSI-2 v3.0 compliance.
• Scientific Imaging: Favor CCDs with on-die CDS and external ADC flexibility if read noise < 2.0 e⁻ is required; verify dark current specs at target operating temperature.
• Automotive Cameras: Require ASIL-B documentation, on-die diagnostics coverage > 90%, and thermal derating curves down to −40 °C.
• Consumer Electronics: Optimize for power-per-MP: IMX990 delivers 0.01 mW per megapixel versus 0.017 mW/Mp for KAI-2020.

Finally, never assume ‘on-chip’ implies ‘optimal’. Cross-check datasheet claims against independent EMVA 1288 reports—many vendors specify SNR under ideal lab conditions (25 °C, 0 lux dark, 1 kHz readout) that don’t reflect real-world deployment. The IMX990’s published 67.5 dB SNR drops to 62.1 dB at 70 °C and 120 fps, a 5.4 dB penalty that must be budgeted in optical design margins.